A Spur-free Fractional-N Sigma-Delta PLL for GSM Applications: Linear Model and Simulations
نویسندگان
چکیده
A new PLL topology and a new simplified linear model are presented The new EA fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
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تاریخ انتشار 2016